this is information on a product in full production. may 2015 docid023119 rev 2 1/9 ESDAVLC6-1BF4 single-line low capacitance transil?, transient surge voltage suppressor (tvs) datasheet - production data features ? bidirectional device ? multiple esd strike sustainability ? very low capacitance: 7 pf max at 0 v ? low leakage current ? ultra small pcb area ? rohs compliant complies with the following standards ? iec 61000-4-2: ? 15 kv (air discharge) ? 8 kv (contact discharge) applications where transient over voltage protection in esd sensitive equipment is required, such as: ? portable multimedia devices and accessories ? notebooks ? digital camera and camcorders ? communication systems ? cellular phone handsets and accessories description the ESDAVLC6-1BF4 is a bidirectional single line tvs diode designed to protect the data lines or other i/o ports against esd transients. the device is ideal for applications where both reduced line capacitance and board space saving are required. figure 1. functional diagram tm: transil is a trademark of stmicroelectronics 0201 package www.st.com
characteristics ESDAVLC6-1BF4 2/9 docid023119 rev 2 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp (1) 1. for a surge greater than the maximum values, the diode will fail in short-circuit. peak pulse voltage iec 61000-4-2 contact discharge iec 61000-4-2 air discharge 15 kv t op operating temperature range -30 to +85 c i pp peak pulse current (8/20 s) 3 a t stg storage temperature range - 55 to +150 c table 2. electrical characteristics (values, t amb = 25 c) symbol test condition min. typ. max. unit v br breakdown voltage, i rm = 1 ma 6 10 v i rm leakage current, v rm = 3 v per line 100 na r d dynamic resistance, pulse width 100 ns 1.7 ? c line line capacitance, f = 1 mhz, v osc 30 mv 4 7 pf v cl +8 kv contact discharge after 30 ns iec 61000 4-2 35 v v i v cl v cl v br v br v rm v rm i rm i pp slope: 1/r d symbol parameter v = breakdown voltage v = stand-off voltage v = clamping voltage i = peak pulse current br rm cl pp i = leakage current @ v rm rm = line capacitance c line
docid023119 rev 2 3/9 ESDAVLC6-1BF4 characteristics 9 figure 3. esd response to iec 61000-4-2 (typical values, +8 kv contact discharge) figure 4. esd response to iec 61000-4-2 (typical values, -8 kv contact discharge) 10 v/div 20 ns/div v : esd peak voltage v :clamping voltage @ 30 ns v :clamping voltage @ 60 ns pp cl cl v :clamping voltage @ 100 ns cl 1 2 3 4 71 v 41 v 25 v 20 v 1 2 4 3 10 v/div 20 ns/div -72 v -40 v -24 v -20 v 1 2 4 3 v : esd peak voltage v :clamping voltage @ 30 ns v :clamping voltage @ 60 ns pp cl cl v :clamping voltage @ 100 ns cl 1 2 3 4 figure 5. junction capacitance versus reverse applied voltage (typical values) figure 6. relative variation of peak pulse power versus initial junction temperature c (pf) 0 1 2 3 4 5 6 7 8 9 10 0123456 f=1 mhz v osc =30mv rms t j =25 c direct / reverse v r (v) p pp (w) 0.0 20.0 40.0 60.0 80.0 100.0 25 35 45 55 65 75 85 95 8/20s direct/reverse t j (c) figure 7. peak pulse power versus exponential pulse duration figure 8. leakage current versus junction temperature (typical values) p pp (w) 1.0 10.0 100.0 1000.0 10 100 1000 t p (s) t = 25 c j direct/reverse 0.01 0.10 1.00 10.00 100.00 25 35 45 55 65 75 85 t j (c) v=v = 3v direct/reverse rrm i r (na)
package information ESDAVLC6-1BF4 4/9 docid023119 rev 2 2 package information ? epoxy meets ul94, v0 ? lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 2.1 0201 package information figure 9. 0201 package outline table 3. 0201 package mechanical data ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.28 0.3 0.32 0.0110 0.0118 0.0126 b 0.125 0.14 0.155 0.0049 0.0055 0.0061 d 0.57 0.6 0.63 0.0224 0.0236 0.0248 d1 0.35 0.0138 e 0.27 0.3 0.33 0.0106 0.0118 0.0130 e1 0.175 0.19 0.205 0.0069 0.0075 0.0081 fd 0.11 0.125 0.14 0.0043 0.0049 0.0055 fe 0.04 0.055 0.07 0.0016 0.0022 0.0028 to p bottom side d e a fd fe b d1 e1
docid023119 rev 2 5/9 ESDAVLC6-1BF4 package information 9 2.2 packing information note: the marking codes can be rotated by 90 or 180 to differentiate assembly location.in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. figure 12. tape and reel outline figure 10. footprint in mm (inches) figure 11. marking 0.243 (0.0096) 0.170 (0.0067) 0.300 (0.0118) 0.243 (0.0096) 0.656 (0.0258) i d bar indicates pin 1 user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 + 0.03 - 0.01 2.0 0.05 1.75 0.1 3.5 0.05 ? 1.5 0.1 0.36 0.03 0.38 0.03 0.22 0.67 0.03 5 5 5 5 5 5 5
recommendation on pcb assembly ESDAVLC6-1BF4 6/9 docid023119 rev 2 3 recommendation on pcb assembly 3.1 stencil opening design 1. general recommendations on stencil opening design a) stencil opening dimensions: l (length), w (width), t (thickness). figure 13. stencil opening dimensions b) general design rule stencil thickness (t) = 75 ~ 125 m 2. recommended stencil window a) stencil opening thickness: 80 m b) other dimensions: see figure 14 figure 14. recommended stencil window position, stencil opening thickness: 80 m l t w aspect ratio w t ----- 1.5 = aspect area lw 2t l w + () --------------------------- - 0.66 = 0.230 (0.0091) 0.183 (0.0072) 0.170 (0.0067) 0.300 (0.0118) 0.285 (0.0112) 0.656 (0.0258) 0.643 (0.0253) footprint stencil window 0.007 (0.00027) 0.007 (0.00027) 0.008 (0.0003) 0.008 (0.0003) mm (inches) 0.243 (0.0096)
docid023119 rev 2 7/9 ESDAVLC6-1BF4 recommendation on pcb assembly 9 3.2 solder paste 1. use halide-free flux, qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste recommended. 3. offers a high tack force to resist component displacement during pcb movement. 4. use solder paste with fine particles: type 4 (powder particle size 20-48 m per ipc j std-005). 3.3 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead rec ognition capabilities of th e placement system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 1.0 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 3.4 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks a nd open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 3.5 reflow profile figure 15. st ecopack ? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
ordering information ESDAVLC6-1BF4 8/9 docid023119 rev 2 4 ordering information figure 16. ordering information scheme 5 revision history table 4. ordering information order code marking package weight base qty delivery mode ESDAVLC6-1BF4 d (1) 1. the marking codes can be rotated by 90 or 180 to differentiate assembly location 0201 0.116 mg 15 000 tape and reel esda vlc 6 - 1 b f4 esda protection device very low capactitance package f4 = 0201 6 = 6 v b = b directional breakdown voltage number of lines directional i table 5. document revision history date revision changes 02-may-2012 1 first issue 20-may-2015 2 updated package graphics and dimensions. updated table 2 and figure 16 . removed internal restriction.
docid023119 rev 2 9/9 ESDAVLC6-1BF4 9 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved
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